A typical random access memory (RAM; e.g., static RAM (SRAM) or dynamic RAM (DRAM)) system for a computer includes an array with one or more columns of SRAM cells configured to store respective logic states, i.e., either a logic high (logical "1") or a logic low (logical "0"). Data is written to and/or read from each of the SRAM cells in each column via differential complimentary bit and nbit connections. An address wordline, which is decoded from a computer address sent by a central processing unit (CPU) or other processor, is communicated to the SRAM cells. The address wordline particularly identifies and enables a specific SRAM cell during each reading and writing operation.
A write driver is designed to write data to a specific SRAM cell that is identified by an address wordline. The bit and nbit connections are initially precharged. In order to write a logic state to a particular SRAM cell, the write driver discharges one of the bit and nbit connections while maintaining the state of the other, in order to create a voltage differential between the connections and instill a particular logic state in the SRAM cell.
A sense amplifier is utilized to retrieve data from SRAM cells. The sense amplifier is typically a differential amplifier. It receives the differential complimentary signals on the bit and nbit connections and can read the stored logic state based upon the voltage differential and polarity between the connections. The sense amplifier produces a data output when prompted to do so by a strobe control signal. The strobe control signal can be a clock edge generated by some type of a timing control unit.
In order to create high-density memories requiring little space, storage elements are often made with the fewest and smallest parts possible. A problem exists, however, in that a high number of decoders are required to access the desired address wordline and column to enable a specific SRAM cell in the array. The use of the large number of decoders imposes a substantial size and component count burden on the chip. Moreover, because the arrays of memory cells in these types of configurations are large, the decoders that are required to drive signals across the arrays to overcome the resistance of the signal wires must also be large. This configuration requires large decoders to maintain the "sweet spot" which is commonly known as the optimal relationship between the resistance of the signal wires to the size of the driver that is required to overcome the resistance. Consequently, the large number of decoders required to properly address the multitude of SRAM cells combined with the requirement that the decoders themselves must be large to maintain the sweet spot, the number of SRAM cells that can be placed on a single chip is substantially limited.
In order to improve the density of SRAM cells relative to speed, a heretofore unaddressed need exists in the industry for an improved SRAM system that increases speed and reduces size and the number of required components in the chip.